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IND16305 40-BIT AC-PDP DRIVER
DESCRIPTION
The IND16305 is an AC plasma display panel (PDP) row driver which uses a high withstand voltage CMOS process. It is composed of a 40-bit bidirectional shift register, latch circuit, and a high withstand voltage CMOS driver block. The logic block operates on a 5 V power supply (CMOS level input), enabling direct connection to a microcomputer. The driver block is implemented by means of 200 V, 400 mA high withstand voltage CMOS.
FEATURES
* * * * * High withstand voltage CMOS structure High withstand voltage, high current output (200 V, 400 mA) On-chip 40-bit bidirectional shift register Low power dissipation (1 mA max. Ta = -40 to +85 C) Wide operating temperature range (-40 to +85 C)
BLOCK DIAGRAM
PC BLK STB
A CLK
I/O
S1
40-Bit Latch
L1
*
O1
40-Bit shift Register
R/L B I/O CLR S40
*
O40
CLR
* High Withstand Voltage CMOS Driver Block 200V, 400mA max
ABSOLUTE MAXIMUM RATINGS (Ta = 25 oC, VSS1 = VSS2 = 0 V) PARAMETER SYMBOL RATING Logic block supply voltage VDD1 -0.5 to +7.0 Driver block supply voltage VDD2 -0.5 to +200 Logic block input voltage VI -0.5 to VDD1 + 0.5 Driver block output current IO 400* Permissible package loss PD 1000 Operating temperature Topt. -40 to +85 Storage temperature Tsrg. -65 to +150
* Duty 1/40. Derate at -10 mW/oC at TA = 25oC or higher
UNIT V V V mA mW o C o C
RECOMMENDED OPERATING PARAMETER Logic block supply voltage Driver block supply voltage Input voltage high Input voltage low Driver output current
CONDITIONS (Ta = -40 to + 85 oC, VSS1 = VSS2 = 0 V) SYMBOL MIN. TYP. MAX. VDD1 4.5 5.0 5.5 VDD2 30 180 VIH 0.8 * VDD1 VDD1 VIL 0 0.2 * VDD1 IO 300
UNIT V V V V mA
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
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IND16305
PIN CONFIGURATION (Top View)
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 VDD2 VSS2 VSS2 VSS1
1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
O40 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 VDD2 VSS2 VSS2 VSS1
* Ensure that the VDD1, VDD2, VSS1 and VSS2 pins are all used, and that VSS1 and VSS2 are used at the same potential (connect at same point near IC). * Pin 33 is connected to the lead frame, and must therefore be left open.
DESCRIPTION OF PINS
Pin Symbol BLK A B CLK STB R/L Pin Name Output blank input RIGHT data input/output LEFT data input/output Clock input Latch enable input Shift direction control input Pin No. 37 30 35 31 36 25 Description See truth table Serial data input/output* When R/L = H A: Input B:Output When R/L = L A: Output B: Input Shift executed on rise H: Latch, L: Data-through H: Right shift modeAO1 ***O40B L : Left shift mode BO40***O1 A CLR PC O1 to O40 VDD1 VDD2 VSS1 VSS2 NC Clear input Polarity reversal input High withstand voltage outputs Logic block power supply Driver block power supply Logic block ground Driver block ground Unused pins 32 27 1 to 20 45 to 64 26, 39 21, 44 24, 41 22, 23, 42, 43 28, 29, 33, 34, 38, 40 L: Shift register ALL L See truth table 200 V, 400 mA max. 5 V 10 % 30 V to 180 V Connect to system GND Connect to system GND at same point. Non-connection Ensure that pin 33 is left open.
* Data resulting from inversion of the data input is input to the shift register, and data resulting from inversion of the shift register data is output to the output.
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
R/L VDD1 PC NC NC A CLK CLR NC NC B STB BLK NC VDD1 NC
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ELECTRICAL SPECIFICATIONS (Ta = 25 C, VDD1 = 4.5 to 5.5 V, VDD2 = 180 V, VSS1 = VSS2 = 0 V) PARAMETER SYMBOL MIN. MAX. UNIT TEST CONDITIONS Output voltage high VOH1 0.9 * VDD1 V Logic IOH = -1 mA Output voltage low VOL1 0.1 * VDD1 V Logic IOL = 1 mA Output voltage high VOH21 160 V O1 to O40, IOH = -150 mA VOH22 140 V O1 to O40, IOH = -300 mA Output voltage low VOL21 20 V O1 to O40, IOL = 150 mA VOL22 40 V O1 to O40, IOL = 300 mA Input current II uA VI = VDD1 or VSS1 1 Input voltage high VIH 0.8 * VDD1 V Input voltage low VIL 0.2 * VDD1 V Static comsumption current IDD1 100 uA Logic Ta = -40 to +85 oC IDD1 10 uA Logic Ta = 25 oC IDD2 1 mA Driver Ta = -40 to +85 oC IDD2 100 uA Driver Ta = 25 oC SWITCHING CHARACTERISTICS (Ta = 25 oC, VDD1 = 5 V, VDD2 = 180 V, Logic CL = 15 pF, Driver CL = 50 pF) PARAMETER SYMBOL MIN. MAX. UNIT TEST CONDITIONS Transmission delay time tPHL1 120 ns CLK A/B tPLH1 120 ns tPLH2 120 ns CLR A/B tPHL3 200 ns CLK O1 to O40 tPLH3 200 ns tPHL4 200 ns STB O1 to O40 tPLH4 200 ns tPHL5 220 ns BLK O1 to O40 tPLH5 220 ns tPHL6 220 ns PC O1 to O40 tPLH6 220 ns Rise time tTLH 100 ns O1 to O40 Fall time tTHL 100 ns O1 to O40 Maximum clock frequency fmax. 15 MHz Duty = 50 % (DATA) Input capacitance CI 15 pF REQUIRED TIMING CONDITIONS (Ta = -40 to +85 oC, VDD1 = 4.5 to 5.5 V) PARAMETER SYMBOL MIN. MAX. UNIT TEST CONDITIONS Clock pulse width PWCLK 30 ns Strobe pulse width PWSTB 60 ns Blank pulse width PWBLK 200 ns PC pulse width PWPC 300 ns Clear pulse width PWCLR 120 ns Data setup time tSETUP 20 ns Data hold time tHOLD 5 ns Clock-strobe time tCLK-STB 120 ns CLK STB
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IND16305
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
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IND16305
TRUTH TABLE 1 (Shift Register Block)
R/L H H L L
STB H L DATA H L H L
CLK H or L H or L
A Input Output
B Output Input
Shift Register Right shift execution Hold Left shift execution Hold
TRUTH TABLE 2 (Latch Block)
Operation Data immediately prior to STB becoming H is held Shift register data is output BLK L L L L H H PC L L H H L H On H L L H H L Remarks
TRUTH TABLE 3 (Driver Block)
All outputs H All outputs L
H: High level L: Low level : H or L DATA: Data input to A (B) Caution To prevent latch up breakdown, the power should be turned on in the order VDD1, logic signal, VDD2. It should be turned off in the opposite order.
TIMING CHART
( ): When R/L=L
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
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IND16305
SWITCHING CHARACTERISTIC WAVEFORMS
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
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IND16305
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
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IND16305
80 PIN PLASTIC QFP (THREE DIRECTIONS) (14x20)
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.30.4 20.00.2 14.00.2 17.60.4 1.0 0.8 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 +0.10 0.15 -0.05 0.10 2.7 0.10.1 5o5o 3.0 MAX. INCHES 0.8780.016 0.7950.009 0.5510.009 0.6930.016 0.039 0.031 0.0140.005 0.006 0.031 (T.P.) 0.071+0.009 0.0310.009 +0.004 0.006 -0.003 0.004 0.106 0.0040.004 5 o5 o 0.119 MAX. P80GF-80-3L9-2
Korzhenevsky 12, Minsk, 220064, Republic of Belarus Fax: +375 (17) 278 28 22 Tel: +375 (17) 278 49 09, 212 27 02 Tel/fax: +375 (17) 212 68 53 E-mail: office@bms.by URL: www.bms.by
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